SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 174

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

6.2.12.6 LPC Interface Signal Definitions
The LPC specification lists seven required and six optional
signals for supporting the LPC interface. Many of the sig-
nals are the same signals found on the PCI interface and
do not require any new pins on the host. Required signals
must be implemented by both hosts and peripherals.
Optional signals may or may not be present on particular
hosts or peripherals.
The Core Logic module incorporates all the required LPC
interface signals and two of the optional signals:
• Required LPC signals:
• Core Logic module optional LPC signals:
174
— LAD[3:0] - Multiplexed Command, Address and Data.
— LFRAME# - Frame: Indicates start of a new cycle,
— LRESET# - Reset: This signal is not available. Use
— LCLK - Clock: This signal is not available. Use PCI 33
— LDRQ# - Encoded DMA/Bus Master Request: Only
— SERIRQ - Serialized IRQ: Only needed by periph-
— LPCPD# - Power Down: Indicates that the peripheral
termination of broken cycle.
PCI Reset signal PCIRST# instead.
MHz clock signal PCICLK instead.
needed by peripheral that need DMA or bus
mastering. Peripherals may not share the LDRQ#
signal.
erals that need interrupt support.
should prepare for power to the LPC interface to be
shut down. Optional for the host.
32579B
6.2.12.7 Cycle Types
Table 6-12 shows the various types of cycles that are sup-
ported by the Core Logic module.
6.2.12.8 LPC Interface Support
The LPC interface supports all the features described in
the LPC Bus Interface specification, revision 1.0, with the
following exceptions:
• Only 8- or 16-bit DMA, depending on channel number.
• Only one external DRQ pin.
Cycle Type
Memory Read
Memory Write
I/O Read
I/O Write
DMA Read
DMA Write
Bus Master Memory Read
Bus Master Memory Write
Does not support the optional larger transfer sizes.
AMD Geode™ SC1200/SC1201 Processor Data Book
Table 6-12. Cycle Types
Supported Sizes
Core Logic Module
1, 2, or 4
1, 2, or 4
(Bytes)
1 or 2
1 or 2
1
1
1
1