SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 226

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

226
Offset 24h-27h
This register is used to indicate configuration for the GPIO signal that is selected in the GPIO Signal Configuration Select Register
(above).
Note:
31:7
5:0
Bit
6
5
PME debouncing, polarity, and edge/level configuration is only applicable on GPIO0-GPIO15 signals (Bank 0 = 00000 to
01111) and on GPIO32-GPIO47 signals (Bank 1 settings of 00000 to 01111). The remaining GPIOs (GPIO16-GPIO31 and
GPIO48-GPIO63) can not generate PMEs, therefore these bits have no function and read 0.
Description
Signal Select. Selects the GPIO signal to be configured in the Bank selected via bit 5 setting (i.e., Bank 0 or Bank 1). See
Table 4-2 "Pin Multiplexing, Interrupt Selection, and Base Address Registers" on page 72 for GPIO ball muxing options.
GPIOs without an associated ball number are not available externally.
Bank 0
000000 = GPIO0 (ball D11)
000001 = GPIO1 (balls D10, N30)
000010 = GPIO2
000011 = GPIO3
000100 = GPIO4
000101 = GPIO5
000110 = GPIO6 (ball D28)
000111 = GPIO7 (ball C30)
001000 = GPIO8 (ball C31)
001001 = GPIO9 (ball C28)
001010 = GPIO10 (ball B29)
001011 = GPIO11 (ball AJ8)
001100 = GPIO12 (ball N29)
001101 = GPIO13 (ball M29)
001110 = GPIO14 (ball D9)
001111 = GPIO15 (ball A8)
Bank 1
100000 = GPIO32 (ball M28)
100001 = GPIO33 (ball L31)
100010 = GPIO34 (ball L30)
100011 = GPIO35 (ball L29)
100100 = GPIO36 (ball L28)
100101 = GPIO37 (ball K31)
100110 = GPIO38 (ball K28)
100111 = GPIO39 (ball J31)
101000 = GPIO40 (ball Y3)
101001 = GPIO41 (ball W4)
101010 = GPIO42
101011 = GPIO43
101100 = GPIO44
101101 = GPIO45
101110 = GPIO46
101111 = GPIO47
Note:
Reserved. Must be set to 0.
PME Debounce Enable. Enables/disables IRQ debounce (debounce period = 16 ms).
0: Disable.
1: Enable. (Default).
See the note in the description of this register for more information about the default value of this bit.
PME Polarity. Selects the polarity of the signal that issues a PME from the selected GPIO signal (falling/low or rising/high).
0: Falling edge or low level input. (Default)
1: Rising edge or high level input.
See the note in the description of this register for more information about the default value of this bit.
Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued)
GPIO63 can be used to generate the PWRBTN# input signal. See PWRBTN# signal description in Section 3.4.16
"Power Management Interface Signals" on page 65.
32579B
GPIO Signal Configuration Access Register (R/W)
Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0
010000 = GPIO16 (ball V31)
010001 = GPIO17 (ball A10)
010010 = GPIO18 (ball AG1)
010011 = GPIO19 (ball C9)
010100 = GPIO20 (balls A9, N31)
010101 = GPIO21
010110 = GPIO22
010111 = GPIO23
011000 = GPIO24
011001 = GPIO25
011010 = GPIO26
011011 = GPIO27
011100 = GPIO28
011101 = GPIO29
011110 = GPIO30
011111 = GPIO31
110000 = GPIO48
110001 = GPIO49
110010 = GPIO50
110011 = GPIO51
110100 = GPIO52
110101 = GPIO53
110110 = GPIO54
110111 = GPIO55
111000 = GPIO56
111001 = GPIO57
111010 = GPIO58
111011 = GPIO59
111100 = GPIO60
111101 = GPIO61
111110 = GPIO62
111111 = GPIO63 (Note)
AMD Geode™ SC1200/SC1201 Processor Data Book
Reset Value: 00000044h