SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 23

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Architecture Overview
• USB: See Section 6.2.4 "Universal Serial Bus" on page
• LPC: See Section 3.4.9 "Low Pin Count (LPC) Bus Inter-
• Sub-ISA: See Section 3.4.8 "Sub-ISA Interface Signals"
• GPIO: See Section 3.4.17 "GPIO Interface Signals" on
More detailed information about each of these interfaces is
provided in Section 6.2 "Module Architecture" on page 142.
• Super/IO Block Interfaces: See Section 4.2 "Pin Multi-
The Core Logic module interface to the GX1 module con-
sists of seven miscellaneous connections, the PCI bus
interface signals, plus the display controller connections.
Note that the PC/AT legacy signals NMI, WM_RST, and
A20M are all virtual functions executed in SMM (System
Management Mode) by the BIOS.
• PSERIAL is a one-way serial bus from the GX1 to the
• IRQ13 is an input from the processor indicating that a
• INTR is the level output from the integrated 8259A PICs
• SMI# is a level-sensitive interrupt to the GX1 that can be
• SUSP# and SUSPA# are handshake signals for imple-
• CPU_RST resets the CPU and is asserted for approxi-
• PCI bus interface signals.
AMD Geode™ SC1200/SC1201 Processor Data Book
147. The USB function uses signal AD29 as the IDSEL
for PCI configuration.
face Signals" on page 60.
on page 59, Section 6.2.5 "Sub-ISA Bus Interface" on
page 147, and Section 4.2 "Pin Multiplexing, Interrupt
Selection, and Base Address Registers" on page 72
page 67.
plexing, Interrupt Selection, and Base Address Regis-
ters" on page 72, Section 3.4.6 "ACCESS.bus Interface
Signals" on page 55, Section 3.4.14 "Fast Infrared (IR)
Port Interface Signals" on page 64, and Section 3.4.13
"Parallel Port Interface Signals" on page 63.
Core Logic module used to communicate power-
management states and VSYNC information for VGA
emulation.
floating point error was detected and that INTR should
be asserted.
and is asserted if an unmasked interrupt request (IRQn)
is sampled active.
configured to assert on a number of different system
events. After an SMI# assertion, SMM is entered and
program execution begins at the base of the SMM
address space. Once asserted, SMI# remains active
until the SMI source is cleared.
menting CPU Clock Stop and clock throttling.
mately 100 µs after the negation of POR#.
2.4
The SuperI/O (SIO) module is a PC98 and ACPI compliant
SIO that offers a single-cell solution to the most commonly
used ISA peripherals.
The SIO module incorporates: two Serial Ports, an Infrared
Communication Port that supports FIR, MIR, HP-SIR,
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284
Parallel Port, two ACCESS.bus Interface (ACB) ports, Sys-
tem Wakeup Control (SWC), and a Real-Time Clock (RTC)
that provides RTC timekeeping.
2.5
In addition to the four main modules (i.e., GX1, Core Logic,
Video Processor and SIO) that make up the SC1200/
SC1201 processor, the following blocks of logic have also
been integrated:
• Clock Generators as described in Section 4.5 "Clock
• Configuration Registers as described in Section 4.2 "Pin
• A WATCHDOG timer as described in Section 4.3
• A High-Resolution timer as described in Section 4.4
2.5.1
This section provides a description of the reset flow of the
SC1200/SC1201 processor.
2.5.1.1
Power-on reset (POR) is triggered by assertion of the
POR# signal. Upon power-on reset, the following things
happen:
• Strap balls are sampled.
• PLL4, PLL5, and PLL6 are reset, disabling their output.
• Certain WATCHDOG and High-Resolution Timer
2.5.1.2
System reset causes signal PCIRST# to be issued, thus
triggering a reset of all PCI and LPC agents. A system
reset is triggered by any of the following events:
• Power-on, as indicated by POR# signal assertion.
• A WATCHDOG reset event (see Section 4.3.2
• Software initiated system reset.
Generators and PLLs" on page 83.
Multiplexing, Interrupt Selection, and Base Address
Registers" on page 72.
"WATCHDOG" on page 79.
"High-Resolution Timer" on page 81.
When the POR# signal is negated, the clocks lock and
then each PLL outputs its clock. PLL6 is the last clock
generator to output a clock. See Section 4.5 "Clock
Generators and PLLs" on page 83.
register bits are cleared.
"WATCHDOG Registers" on page 80).
SuperI/O Module
Clock, Timers, and Reset Logic
Reset Logic
Power-On Reset
System Reset
32579B
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