SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 95

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

SuperI/O Module
Table 5-3 provides the bit definitions for the Standard Con-
figuration registers.
• All reserved bits return 0 on reads, except where noted
AMD Geode™ SC1200/SC1201 Processor Data Book
Index 07h
This register selects the current logical device. See Table 5-2 for valid numbers. All other values are reserved.
Index 20h-2Fh
SIO configuration and ID registers. See Section 5.4.1 "SIO Control and Configuration Registers" on page 97 for register/bit details.
Index 30h
Index 60h
Index 61h
Index 62h
Index 63h
Index 70h
Index 71h
Selects the type and level of the interrupt request number selected in the previous register.
Index 74h
Selects selected DMA channel for DMA 0 of the logical device (0 - the first DMA channel in case of using more than one DMA channel).
otherwise. They must not be modified as such modifica-
tion may cause unpredictable results. Use read-modify-
Bit
7:0
7:1
7:0
7:0
7:0
7:0
7:4
3:0
7:2
7:3
2:0
0
1
0
Description
Logical Device number.
Reserved.
Logical Device Activation Control.
0: Disable
1: Enable
Descriptor 0 A[15:8]. Selects I/O lower limit address bits [15:8] for I/O Descriptor 0.
Descriptor 0 A[7:0]. Selects I/O lower limit address bits [7:0] for I/O Descriptor 0.
Descriptor 1 A[15:8]. Selects I/O lower limit address bits [15:8] for I/O Descriptor 1.
Descriptor 1 A[7:0]. Selects I/O lower limit address bits [7:0] for I/O Descriptor 1.
Reserved.
Interrupt Number. These bits select the interrupt number. A value of 1 selects IRQ1, a value of 2 selects IRQ2, etc. (up to
IRQ12).
Note: IRQ0 is not a valid interrupt selection.
Reserved.
Interrupt Level Requested. Level of interrupt request selected in previous register.
0: Low polarity.
1: High polarity.
This bit must be set to 1 (high polarity), except for IRQ8#, that must be low polarity.
Interrupt Type Requested. Type of interrupt request selected in previous register.
0: Edge.
1: Level.
Reserved.
DMA 0 Channel Select. This bit field selects the DMA channel for DMA 0.
The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
Values 5-7 are reserved.
I/O Port Base Address Bits [15:8] Descriptor 0 (R/W)
I/O Port Base Address Bits [15:8] Descriptor 1 (R/W)
Table 5-3. Standard Configuration Registers
I/O Port Base Address Bits [7:0] Descriptor 0 (R/W)
I/O Port Base Address Bits [7:0] Descriptor 1 (R/W)
Interrupt Request Type Select (R/W)
Logical Device Number (R/W)
DMA Channel Select 0 (R/W)
SIO Configuration (R/W)
Interrupt Number (R/W)
Activate (R/W)
• Write only registers should not use read-modify-write
write to prevent the values of reserved bits from being
changed during write.
during updates.
32579B
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