SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 351

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Video Processor Module - Video Processor Registers - Function 4
AMD Geode™ SC1200/SC1201 Processor Data Book
Offset 414h-417h
Offset 418h-41Bh
Offset 41Ch-41Fh
Offset 420h-423h
31:27
26:16
15:11
31:20
31:20
31:24
10:0
19:0
19:0
21:9
Bit
23
22
8
7
6
5
4
3
2
Table 7-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Description
Reserved.
VBI_H_END (VBI Horizontal End). Specifies the horizontal end position for VBI data sent to the encoder.
Reserved.
VBI_H_START (VBI Horizontal Start). Specifies the horizontal start position for VBI data sent to the encoder.
Reserved.
VBI_TOTAL_COUNT_ODD (VBI Odd Fields Total Count). Specifies the total count of VBI data in bytes for odd fields. This
field is used to separate VBI data from active video data when both types of data are received from the GX1 module’s video
port.
Reserved.
VBI_TOTAL_COUNT_EVEN (VBI Even Fields Total Count). Specifies the total count of VBI data in bytes for even fields.
This field is used to separate VBI data from active video data when both types of data are received from the GX1 module’s
video port.
Reserved. Must be set to 0.
ODD_TO (Odd Field Time Out). Indicates CGENTO0 (F4BAR0+Memory Offset 43Ch[15:0]) has expired. This bit can be
reset by writing 1 to it.
EVEN_TO (Even Field Time Out). Indicates CGENTO1 (F4BAR0+Memory Offset 43Ch[31:16]) has expired. This bit can
be reset by writing 1 to it.
Reserved.
GENLOCK_TO_ENC_TIMING (GenLock to Encoder Timing). Selects the timing to which the GX1 module’s vertical tim-
ing needs to be synchronized.
0: VIP vertical timing.
1: Encoder vertical timing. The TV encoder generates a reference for GenLock at the start of line 1 of its counters.
Reserved. Set to 0.
RST_ENC_BFOR_DLY (Reset Encoder Before Delay). Selects the position of the encoder reset with respect to the pro-
grammed VIP_VSYNC edge and delay.
0: The encoder is reset after the programmed delay.
1: The encoder is reset before the programmed delay.
FIELD_EVEN (Encoder Field Even). Used in conjunction with bit 0 of this register for single GenLock field synchronization.
0: Encoder field is set to odd.
1: Encoder field is set to even.
GENLOCK_TOUT_EN (GenLock Timeout Enable).
0: Disable.
1: Enable timeout.
VIP_VSYNC_EDGE_SEL (VIP VSYNC Edge Select). Selects which edge of the VSYNC signal should be synchronized
with VIP.
0: Rising edge.
1: Falling edge.
GX1_VSYNC_EDGE_SEL (GX1 VSYNC Edge Select). Selects which edge of the VSYNC signal should be synchronized
with the GX1 module.
0: Rising edge.
1: Falling edge.
VBI Horizontal Control Register (R/W)
VBI Total Count Register - Even (R/W)
VBI Total Count Register - Odd (R/W)
GenLock Register (R/W)
32579B
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
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