SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 200

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

200
Index 60h-63h
Index 64h-6Bh
Index 6Ch-6Fh
Note:
Index 70h-71h
Index 72h
This register is used in conjunction with F0 Index 70h (IOCS1# Base Address register).
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued)
31:16
31:8
15:8
15:0
Bit
7:4
3:0
7
6
5
4
3
2
1
0
7
Register must be read/written as a DWORD.
Description
Reserved. Must be set to 0.
SUSP_3V Shut Down PLL5. Allow internal SUSP_3V to shut down PLL5.
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
SUSP_3V Shut Down PLL4. Allow internal SUSP_3V to shut down PLL4
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
SUSP_3V Shut Down PLL3. Allow internal SUSP_3V to shut down PLL3.
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
SUSP_3V Shut Down PLL2. Allow internal SUSP_3V to shut down PLL2.
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
SUSP_3V Shut Down PLL6. Allow internal SUSP_3V to shut down PLL6.
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
ACPI C3 SUSP_3V Enable. Allow internal SUSP_3V to be active during C3 state.
0: Disable.
1: Enable.
ACPI SL1 SUSP_3V Enable. Allow internal SUSP_3V to be active during SL1 sleep state.
0: Disable.
1: Enable.
ACPI C3 Support Enable. Allow support of C3 states.
0: Disable.
1: Enable.
Reserved. Must be written to 0.
Reserved. Must be written to FFh.
ROM Size. If F0 Index 52h[2] = 1:
0000: 16 MB = FF000000h-FFFFFFFFh
1000: 8 MB = FF800000h-FFFFFFFFh
1100: 4 MB = FFC00000h-FFFFFFFFh
Reserved. Must be written to 0.
I/O Chip Select 1 Base Address. This 16-bit value represents the I/O base address used to enable assertion of IOCS1#
(ball D10 or N30 - see PMR[23] in Table 4-2 on page 72).
This register is used in conjunction with F0 Index 72h (IOCS1# Control register).
I/O Chip Select 1 Positive Decode (IOCS1#).
0: Disable.
1: Enable.
32579B
IOCS1# Base Address Register (R/W)
IOCS1# Control Register (R/W)
ACPI Control Register (R/W)
ROM Mask Register (R/W)
Reserved
1110: 2 MB = FFE00000h-FFFFFFFFh
1111: 1 MB = FFF00000h-FFFFFFFFh
All other settings for these bits are reserved.
Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0
AMD Geode™ SC1200/SC1201 Processor Data Book
Reset Value: 0000FFF0h
Reset Value: 00000000h
Reset Value: 0000h
Reset Value: 00h
Reset Value: 00h