SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 78

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

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Offset 38h
This register selects the IRQ signal of the combined WATCHDOG and High-Resolution timer interrupt. This interrupt is shareable with
other interrupt sources.
Offset 39h-3Bh
Offset 3Ch
This register identifies the device. SC1200 = 04h. SC1201 = 05h.
Offset 3Dh
This register identifies the device revision. See the AMD Geode™ SC1200/SC1201 Processor Specification Update document for value.
Offset 3Eh-3Fh
This register sets the base address of the Configuration block.
15:6
Bit
2:1
7:4
3:0
5:0
3
0
Table 4-2. Pin Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Description
BUS16 (16-Bit Wide Boot Memory). (Read Only) This bit reports the status of the BOOT16 strap (ball C8). If the BOOT16
strap is pulled high, at reset 16-bit access to ROM in the Sub-ISA interface is enabled. MCR[14] = 1 inverts the meaning of
this register.
0: 8-bit wide ROM.
1: 16-bit wide ROM.
Reserved. Write as read.
SDBE0 (Slave Disconnect Boundary Enable). Works in conjunction with the GX1 module’s PCI Control Function 2 Regis-
ter (Index 41h), bit 1 (SDBE1). Sets boundaries for when the GX1 module is a PCI slave.
SDBE[1:0]
00: Read and Write disconnect on boundaries set by bits [3:2] of the GX1 module’s PCI Control Function 2 register (Index
01: Write disconnects on boundaries set by bits [3:2] of the GX1 module’s PCI Control Function 2 register. Read discon-
1x: Read and Write disconnect on cache line boundary of 16 bytes.
This bit is reset to 1.
All PCI bus masters (including SC1200/SC1201 processor’s on-chip PCI bus masters, e.g., the USB Controller) must be dis-
abled while modifying this bit. When accessing this register while any PCI bus master is enabled, use read-modify-write to
ensure these bit contents are unchanged.
Reserved. Write as read.
CBIRQ. Configuration Block Interrupt.
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
Configuration Base Address. These bits are the high bits of the Configuration Base Address.
Configuration Base Address. These bits are the low bits of the Configuration Base Address. These bits are set to 0.
41h).
nects on cache line boundary of 16 bytes.
32579B
Configuration Base Address Register - CBA (RO)
Device Identification Number Register - ID (RO)
Interrupt Selection Register - INTSEL (R/W)
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
Revision Register - REV (RO)
Reserved - RSVD
1000: IRQ8#
1001: IRQ9
1010: IRQ10
1011: IRQ11
AMD Geode™ SC1200/SC1201 Processor Data Book
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
General Configuration Block
Reset Value: 00h
Reset Value: xxh
Reset Value: xxh
Reset Value: xxh