SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 255

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Core Logic Module - SMI Status and ACPI Registers - Function 1
AMD Geode™ SC1200/SC1201 Processor Data Book
Offset 18h-1Bh
Offset 1Ch-1Fh
Note:
Offset 20h
Offset 21h-FFh
The read value for these registers is undefined.
31:17
15:12
31:24
23:0
Bit
7:4
3:0
7:1
16
11
10
9
8
0
This register can also be read at F1BAR0+I/O Offset 1Ch.
Description
Reserved.
PCTL_DELAYEN. Allow staggered delays on the activation and deactivation of the power control pins PWRCNT1,
PWRCNT2, and ONCTL# by 2 msec each.
0: Disable. (Default)
1: Enable.
Reserved. Must be set to 0.
PLVL3_SMIEN. Allow SMI generation when the PLVL3 Register (F1BAR1+I/O Offset 05h) is read.
0: Disable.
1: Enable. (Default)
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[4].
Reserved. Must be set to 0.
SLP_SMIEN. Allow SMI generation when the SLP_EN bit (F1BAR1+I/O Offset 0Ch[13]) is set.
0: Disable.
1: Enable. (Default)
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[2].
THT_SMIEN. Allow SMI generation when the THT_EN bit (F1BAR1+I/O Offset 00h[4]) is set.
0: Disable.
1: Enable. (Default)
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[1].
Reserved. Must be set to 0.
SCI_IRQ_ROUTE. SCI is routed to:
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
For more details see Section 6.2.6.3 "Programmable Interrupt Controller" on page 155.
Reserved.
TMR_VAL. (Read Only) This bit field contains the running count of the power management timer.
Reserved.
Arbiter Disable. Disables the PCI arbiter when set by the OS. Used during C3 transition.
0: Arbiter not disabled. (Default)
1: Disable arbiter.
Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
0100: IRQ4
0101: IRQ5
0010: IRQ6
0011: IRQ7
PM2_CNT — PM2 Control Register (R/W)
PM_TMR — ACPI Timer Register (RO)
ACPI SCI_ROUTING Register (R/W)
Reserved
1000: IRQ8#
1001: IRQ9
1010: IRQ10
1011: IRQ11
32579B
1100: IRQ12
1101: IRQ13
1110: IRQ14
1111: IRQ15
Reset Value: 00000F00h
Reset Value: xxxxxxxxh
Reset Value: 00h
Reset Value: 00h
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