SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 56

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

3.4.7
56
Signal Name
INTA#
INTB#
INTC#
INTD#
PAR
FRAME#
IRDY#
TRDY#
PCI Bus Interface Signals (Continued)
BalL No.
32579B
D26
C26
AA2
C9
D8
F2
F1
J4
Type
I/O
I/O
I/O
I/O
I
Description
PCI Interrupts. The SC1200/SC1201 processor pro-
vides inputs for the optional “level-sensitive” PCI inter-
rupts (also known in industry terms as PIRQx#). These
interrupts can be mapped to IRQs of the internal 8259A
interrupt controllers using PCI Interrupt Steering Regis-
ters 1 and 2 (F0 Index 5Ch and 5Dh).
Note:
Parity. Parity generation is required by all PCI agents.
The master drives PAR for address- and write-data
phases. The target drives PAR for read-data phases. Par-
ity is even across AD[31:0] and C/BE[3:0]#.
For address phases, PAR is stable and valid one PCI
clock after the address phase. It has the same timing as
AD[31:0] but is delayed by one PCI clock.
For data phases, PAR is stable and valid one PCI clock
after either IRDY# is asserted on a write transaction or
after TRDY# is asserted on a read transaction.
Once PAR is valid, it remains valid until one PCI clock
after the completion of the data phase. (Also see
PERR#.)
Frame Cycle. Frame is driven by the current master to
indicate the beginning and duration of an access.
FRAME# is asserted to indicate the beginning of a bus
transaction. While FRAME# is asserted, data transfers
continue. FRAME# is de-asserted when the transaction
is in the final data phase.
This signal is internally connected to a pull-up resistor.
Initiator Ready. IRDY# is asserted to indicate that the
bus master is able to complete the current data phase of
the transaction. IRDY# is used in conjunction with
TRDY#. A data phase is completed on any PCI clock in
which both IRDY# and TRDY# are sampled as asserted.
During a write, IRDY# indicates that valid data is present
on AD[31:0]. During a read, it indicates that the master is
prepared to accept data. Wait cycles are inserted until
both IRDY# and TRDY# are asserted together.
This signal is internally connected to a pull-up resistor.
Target Ready. TRDY# is asserted to indicate that the tar-
get agent is able to complete the current data phase of
the transaction. TRDY# is used in conjunction with
IRDY#. A data phase is complete on any PCI clock in
which both TRDY# and IRDY# are sampled as asserted.
During a read, TRDY# indicates that valid data is present
on AD[31:0]. During a write, it indicates that the target is
prepared to accept data. Wait cycles are inserted until
both IRDY# and TRDY# are asserted together.
This signal is internally connected to a pull-up resistor.
If selected as INTC# or INTD# function(s) but not
used, tie INTC# and INTD# high.
AMD Geode™ SC1200/SC1201 Processor Data Book
GPIO19+IOCHRDY
IDE_DATA7
Signal Definitions
Mux
D12
D14
D13
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