ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 100

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

ST52510xx ST52513xx
15.4.2 Slave Configuration.
In slave configuration, the serial clock is received
on the SCK pin from the master device.
The value of the SPR0, SPR1 and SPR2 bits is not
used for data transfer.
Procedure
– For correct data transfer, the slave device must
– The SS pin must be connected to a low level sig-
– Clear the MSTR bit and set the SPE bit to assign
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Transmit Sequence
The data byte is loaded into the 8-bit shift register
(from the internal bus) during a write cycle and
then shifted out serially to the MISO pin most
significant bit first.
The transmit sequence begins when the slave
device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPI_IN register is
read, the SPI peripheral returns the buffer value.
The SPIF bit is cleared by the following software
sequence:
1. An access to the SPI_STATUS_CR register
2. A read to the SPI_IN register.
Note: While the SPIF bit is set, all writes to the
SPI_OUT
SPI_STATUS_CR register is read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see
Depending on the CPHA bit, the SS pin has to be
set to write to the SPI_OUT register between each
data byte transfer to avoid a write collision (see
Section
15.4.3 Data Transfer Format.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
100/136
be in the same timing mode as the master de-
vice (CPOL and CPHA bits). See
nal during the complete byte transmit sequence,
if this pin is used.
the pins to alternate function.
while the SPIF bit is set.
15.4.4).
register
Section
are
15.4.6).
inhibited
Figure
until
15.4.
the
(shifted in serially). The serial clock is used to
synchronize data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; the other slave devices that are not
selected do not interfere with SPI transfer.
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady
state value of the clock when data isn’t being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits select the data capture clock
edge.
Figure
combinations of the CPHA and CPOL bits. The
diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
A write collision should not occur even if the SS pin
stays low during a transfer of several bytes (see
Figure
CPHA bit is reset
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the
occurrence of the first clock transition.
The SS pin must be toggled high and low between
each byte transmitted (see
In order to protect the transmission from a write
collision a low value on the SS pin of a slave device
freezes the data in its SPI_OUT register and does
not allow it to be altered. Therefore, the SS pin
must be high to write a new data byte in the
SPI_OUT without producing a write collision.
15.4.4 Write Collision Error.
15.3).
15.4, shows an SPI transfer with the four
Figure
15.3).