ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 91

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

Slave address transmission
At this point, the slave address is sent to the SDA
line via the internal shift register.
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the
following event:
– The EVF and ADD10 bit is set by hardware with
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_OUT register, holding the SCL line low (see
Figure 14.3
The second address byte is sent by the interface.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_CR register (for example set PE bit), holding
the SCL line low (see
sequencing EV6).
Next, the master must enter Receiver or
Transmitter mode.
Note: In 10-bit addressing mode, in order to switch
the master to Receiver mode, software must
generate a repeated Start condition and resend the
header sequence with the least significant bit set
(11110xx1).
Master Receiver
Following the address transmission and after
I2C_SR1 and I2C_CR registers have been
accessed, the master receives bytes from the SDA
line into the I2C_IN register via the internal shift
register. After each byte the interface generates in
sequence:
– Acknowledge pulse if the ACK bit is set
– EVFand BTF bits are set by hardware with an in-
Afterwards, the interface waits for a read of the
I2C_SR1 register followed by a read of the I2C_IN
register, holding the SCL line low (see
14.3
interrupt generation if the ITE bit is set.
generation if the ITE bit is set.
terrupt if the ITE bit is set.
Transfer sequencing EV7).
Transfer sequencing EV9).
Figure 14.3
Transfer
Figure
In order to close the communication: before
reading the last byte from the I2C_IN register, set
the STOP bit to generate the Stop condition. The
interface automatically goes back to slave mode
(M/SL bit cleared).
Note: In order to generate the non-acknowledge
pulse after the last data byte received, the ACK bit
must be cleared just before reading the second last
data byte.
Master Transmitter
Following the address transmission and after the
I2C_SR1 register has been read, the master sends
bytes from the I2C_OUT register to the SDA line
via the internal shift register.
The master waits for a read of the I2C_SR1
register followed by a write in the I2C_OUT
register, holding the SCL line low (see
14.3
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
In order to close the communication: after writing
the last byte to the I2C_OUT register, set the
STOP bit to generate the Stop condition. The
interface automatically returns to slave mode (M/
SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
– AF: Detection of a non-acknowledge bit. In this
– ARLO: Detection of an arbitration lost condition.
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. Both lines must
be released via software.
is set.
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
In this case the ARLO bit is set by hardware
(with an interrupt if the ITE bit is set and the in-
terface automatically goes back to slave mode
(the M/SL bit is cleared).
Transfer sequencing EV8).
ST52510xx ST52513xx
Figure
91/136