ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 40

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

ST52510xx ST52513xx
4.7 In-Situ Programming (ISP)
The Program/Data Memory can be programmed
using the ISP mode. This mode allows the device
to be programmed when it is mounted in the user
application board.
This feature can be implemented by adding a
minimum number of components and board
impact.
The programming procedures and pins used are
identical to the ones described before for the
standard Programming Mode. All the features
previously described in this chapter are applicable
in ISP mode.
If RESET, SCL and SDA pins are used in the user
application board for other purposes, it is
recommended to provide an adequate isolation to
avoid a conflict when the other devices force the
signal level.
The ISP can be applied by using the standard tools
for the device programming. The ST52F510/F513
Starter Kit supplies a cable to perform the ISP. The
user application board should supply a suited
connector type for the cable (see Starter Kit User
Manual).
4.8 In-Application Programming (IAP)
The In Application Programming Mode (IAP)
allows the writing of user data in the Flash and
EEPROM memories when the user program is
running.
There are two ways to write data in IAP mode:
single byte write and Block write. Both procedures
take about 4.5 ms to complete the writing: the
Block write allows the writing of 32 byte in parallel.
Remark: during data writing, the execution of the
user program is stopped until the procedure is
completed. Interrupt requests stop the writing
operation and the data may be not stored. The bit
ABRT in the IAP_SR Input register signals that the
data writing hasn’t been completed. To assure
writing completion, the user should globally disable
the interrupts (UDGI instruction) before starting
IAP data writing.
4.8.1 Single byte write. Writing of a single byte in
the
performed by using the LDER instructions (both
direct and indirect addressing). The memory page
should be indicated before the LDER instruction
with the PGSET or PGSETR instruction. The byte
address inside the page is specified by the LDER
instruction itself.
As soon as the instruction is executed, the data
writing starts and is performed in about 4.5 ms.
40/136
Non-Volatile
Program/Data
memory
is
4.8.2 Block write. This procedure allows the
writing of 32 bytes in parallel. These bytes should
belong to the same block.
Before the writing in the Program/Data memory,
data must be buffered in the Register File in the
first 32 locations (0-31, 00h-020h) by using the
normal instructions to load the Register File
locations.
Then the data writing starts by using the BLKSET
instruction. The destination block is addressed by
specifying the memory page with the PGSET or
PGSETR instruction before to start the writing; the
block inside the page is addressed with the
argument of the BLKSET instruction.
Example:
This instruction sequence writes the contents of
the first 32 bytes of the Register File in the
locations 1408-1439 (0580h-059Fh).
Warning: the user should be careful in specifying
the correct page and block: the addressing of an
not existing block can cause the unwanted writing
of a different block.
As soon as the BLKSET instruction is executed,
the data writing starts and is performed in about
4.5 ms.
This procedure may also be used to write few data,
taking in account that all the 32 byte are written in
the block anyway.
4.8.3 Memory Corruption Prevention.
The user can protect some pages (or all the
memory) from unintentional writings. The only
constraint is that the protected pages must be
consecutive.
Two Option Bytes allow the specification of the
page to be protected: PG_LOCK (Option Byte 5)
and PG_UNLOCK (Option Byte 6). PG_LOCK is
used
PG_UNLOCK is used to specify the first page not
protected after the protected ones. The pages
between the two addresses are protected.
When writing in a protected page is attempted, the
procedure is aborted and the bit PRTCD of
IAP_SR Input register is set.
If the PG_LOCK and PG_UNLOCK have the same
value, no page is protected.
In Programming Mode the protection is not
considered and the pages can be written unless
the device is locked.
PGSET 5
BLKSET 4
to
specify
the
first
protected
page;