ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 95

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

Bit 6-0: CC6-CC0 7-bit clock divider
Warning: For safety reason, CC6-CC0 bits must
be configured with a value >= 3 for the Standard
mode and >=2 for the Fast mode.
I
Configuration Register 18 (012h) Read/Write
Reset Value: 0000 0000 (00h)
7-bit Addressing Mode
bit 7-1: ADD7-ADD1 Interface address.
Bit 0: ADD0 Address direction bit.
Note: Address 01h is always ignored.
10-bit Addressing Mode
bit 7-0: ADD7-ADD0 Interface address.
2
ADD7
C Own Address Register 1 (I2C_OAR1)
7
– Standard mode (FM/SM=1): F
– Fast mode (FM/SM=0): F
1: Standard I
0: Fast I
These bits select the speed of the bus (F
depending on the I
cleared when the interface is disabled
(PE=0). The speed can be computed as
follows:
These bits define the I
interface. They are not cleared when the
interface is disabled (PE=0).
This bit is “don’t care”, the interface
acknowledges either 0 or 1. It is not cleared
when the interface is disabled (PE=0).
These are the least significant bits of the I
bus address of the interface. They are not
cleared when the interface is disabled
(PE=0).
F
F
ADD6
SCL
SCL
100 kHz)
kHz)
= f
= f
ADD5
2
CPU
CPU
C Mode (recommended up to 400
/(3x[CC6..CC0]+11)
/(2x[CC6..CC0]+9)
2
C Mode (recommended up to
ADD4
2
ADD3
C mode. They are not
2
C bus address of the
SCL
ADD2
> 100kHz
SCL
ADD1
<= 100kHz
ADD0
SCL
0
2
C
)
I
Configuration Register 19 (013h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-3: Not Used
bit 2-1: ADD9-ADD8 Interface address.
Bit 0: Reserved, it must be left to 0.
14.5.2 I
I
Input Register 6 (06h) Read only
Reset Value: 0000 0000 (00h)
bit 7-0: I2CDI7-I2CDI0 Received data.
These bits contain the byte to be received from the
bus in Receiver mode: the first data byte is
received automatically in the I2C_IN register using
the least significant bit of the address.
Then, the next data bytes are received one by one
after reading the I2C_IN register.
I
Input Register 7 (07h) Read only
Reset Value: 0000 0000 (00h)
2
2
2
I2CDI7
C Own Address Register 2 (I2C_OAR2)
C Data Input Register (I2C_IN)
C Status Register 1 (I2C_SR1)
EVF
7
7
7
-
These are the most significant bits of the I
bus address of the interface (10-bit mode
only). They are not cleared when the
interface is disabled (PE=0).
ADD10
I2CDI6
2
-
C Interface Input Registers.
I2CDI5
TRA
-
I2CDI4
BUSY
-
ST52510xx ST52513xx
I2CDI3
BTF
-
I2CDI2
ADD9
ADSL
2
I2CDI1
ADD8
M/SL
95/136
I2CDI0
SB
0
0
0
-
2
C