ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 121

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

16.12.4 Static and Dynamic Latch-up.
■
Figure 16.10 Simplified Diagram of the ESD Generator for DLU
Notes:
1. Class description: Class A is an STMicroelectronics internal specification. All its limits are higher than
16.12.5 ESD Pin Protection Strategy. In order
to protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit
elements. Stress generally affects the circuit
elements, which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements that are to
be protected must not receive excessive current,
voltage, or heating within their structure.
An ESD network combines the different input and
output protections. This network works by allowing
safe discharge paths for the pins subject to ESD
stress. Two critical ESD stress cases are
presented in
standard pins.
LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed on
each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard.
the JEDEC specification, that means when a device belongs to Class A it exceeds the JEDEC standard.
Class B strictly covers all the JEDEC criteria (international standard).
Symbol
DLU
LU
Static latch-up class
Dynamic latch-up class
ESD
GENERATOR
Figure 16.11
R
Parameter
CH
= 50 M
C
S
and
= 150 pF
Figure 16.12
R
D
= 330
for
HV RELAY
DISCHARGE
RETURN CONNECTION
V
DD
■
Standard Pin Protection
In order to protect the output structure the following
elements are added:
- A diode to V
- A protection device between V
In order protect the input structure the following
elements are added:
- A resistor in series with pad (1)
- A diode to V
- A protection device between V
=5.5V, f
DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in
DISCHARGE TIP
Conditions
OSC
T
T
A
A
=25 C
=85 C
= 8 MHz, T
DD
DD
(3a) and a diode from V
(2a) and a diode from V
ST FIVE
A
=25 C
ST52510xx ST52513xx
V
V
DD
SS
DD
DD
Figure
and V
and V
Class
16.10.
SS
SS
A
A
A
SS
SS
121/136
1)
(3b)
(2b)
(4)
(4)