ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 62

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

ST52510xx ST52513xx
9 INSTRUCTION SET
ST52F510/F513 supplies 107 (98 + 9 Fuzzy)
instructions that perform computations and control
the device. Computational time required for each
instruction consists of one clock pulse for each
Cycle plus 2 clock pulses for the decoding phase.
Total computation time for each instruction is
reported in
The
multiplication
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
Figure
Division is performed between a 16 bit dividend
and an 8 bit divider, the result and the remainder
are stored in two 8-bit registers (see
9.1 Addressing Modes
ST52F510/F513 instructions allow the following
addressing modes:
■
■
■
Table 9.1 Instruction Set
62/136
Inherent: this instruction type does not require
an operand because the opcode specifies all the
information necessary to carry out the
instruction. Examples: NOP, SCF.
Immediate: these instructions have an operand
as a source immediate value. Examples: LDRC,
ADDI.
Direct: the operands of these instructions are
specified with the direct addresses. The
Mnemonic
BLKSET
GETPG
LDCNF
LDCE
LDCR
LDER
LDER
LDER
LDER
LDFR
LDCI
ALU
2.3.
Table 9.1
of
(MULT)
ST52F510/F513
LDER memx,(regy)
LDER (regx),(regy)
LDCE confx,memy
LDER memx, regy
LDFR fuzzyx, regy
LDER (regx), regy
LDCNF regx, conf
LDCR confx, regy
LDCI confx, const
BLKSET const
GETPG regx
Instruction
and
division
can
Figure
Bytes
perform
2.4).
Load Instructions
2
3
3
3
3
3
3
2
3
3
3
(DIV).
■
■
9.2 Instruction Types
ST52F510/F513 supplies the following instruction
types:
■
■
■
■
■
■
The instructions are listed in
Cycles
8/10
operands can refer (according to the opcode) to
addresses belonging to the different addressing
spaces. Example: SUB, LDRE.
Indirect: data addresses that are required are
found in the locations specified as operands.
Both source and/or destination operands can be
addressed indirectly. The operands can refer,
(according to the opcode) to addresses
belonging to different addressing spaces.
Examples: LDRR(reg1),(reg2);
Bit Direct: operands of these instructions directly
address the bits of the specified Register File
locations. Examples: BSET, BTEST.
Load Instructions
Arithmetic and Logic Instructions
Bitwise instructions
Jump Instructions
Interrupt Management Instructions
Control Instructions
12
12
(*)
11
11
7
7
7
8
8
LDER mem_addr,(reg1).
Z
-
-
-
-
-
-
-
-
-
-
-
Table 9.1
S
-
-
-
-
-
-
-
-
-
-
-
C
-
-
-
-
-
-
-
-
-
-
-