ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 52

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

ST52510xx ST52513xx
7 I/O PORTS
7.1 Introduction
ST52F510/F513 are characterized by flexible
individually programmable multi-functional I/O
lines. The ST52F510/F513 supplies devices with
up to 3 Ports (named from A to C) with up to 22 I/
O lines.
Each pin can be used as a digital I/O or can be
connected with a peripheral (Alternate Function).
The I/O lines belonging to Port A and Port B can
also be used to generate Port Interrupts. The I/O
Port pins can be configured in the following modes:
■
■
■
■
■
■
■
■
These
programming three Configuration Registers for
each Port. All the pins that belong to the same Port
can be configured separately by setting the
corresponding bits in the three registers (see
Register Description).
To avoid side effects, the Configuration Registers
are latched only when the Data Direction Register
(PORT_x_DDR) is written. For this reason this
register must be always written when modifying the
pin configuration. All the I/O digital pins are TTL
compatible and have a Schmitt Trigger. The output
buffer can supply high current sink (up to 8mA).
Note: With the aim to reduce current consumption
it is recommended that no floating pins are left; all
unused pins must be kept at fixed voltage.
Furthermore it is recommended that bits of IO
Configuration Registers related to not used or non
available port/pins are set as Input Pull-Up.
Figure 7.1 Digital Pin
52/136
DIG ITAL O UT
Input high impedance (reset state)
Input with pull-up
Output with pull-up
Output push-pull
Output with weak pull-up
Output open drain
Interrupt with pull-up
Interrupt without pull-up
ENAB LE
P ULL UP
EN ABLE
DATA
DATA
O UT
IN
eight
modes
can
be
PA D
selected
PO RT A ,C,D,E
PIN
by
7.2 Input Mode
The pins configured as input can be read by
accessing the corresponding Port Input Register
by means of the LDRI instruction. The addresses
for Port A, B and C are respectively 0 (00h), 1
(01h), and 2 (02h).
When executing the LDRI instruction all the signals
connected to the input pins of the Port are read and
the logical value is copied in the specified Register
File location. If some pins are configured in output,
the port buffer contents, which are the last written
logical values in the output pins, are read.
7.3 Output Mode
The pins configured as output can be written by
accessing the corresponding Port Output Register
by means of the LDPR, LDPI and LDPE
instructions. The addresses for Port A, B and C are
respectively, 0 (00h), 1 (01h), and 2 (02h).
When executing the above mentioned instructions,
the Port buffer is written and the Port pin signals
are modified. If some pins are configured as input
or as interrupt, the values are ignored.
7.4 Interrupt Mode
The pins configured as Interrupt Mode can
generate a Port Interrupt request. Only Port A and
Port B pins can be configured in this mode.
An Interrupt vector is associated to each Port:
there are two Port Interrupts available but more
pins of the ports can act as source at the same
time.
The Configuration Registers switch the signals
deriving from interrupt pins to an OR gate that
generates the interrupt request signal. The signal
deriving from the pins can be read, allowing the
discrimination of the interrupt sources when more
than one pin can generate the interrupt signal.
The interrupt trigger can be configured either in the
rising or falling edge of the external signal by using
the INT_POL register
Figure 7.2 Analog Pin