ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 47

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

6.2 Reset
Four Reset sources are available:
■
■
■
■
When a Reset event occurs, the user program
restarts from the beginning.
6.2.1 External Reset. Reset is an input pin. An
internal reset does not affect this pin. A Reset
signal
recognized immediately. The RESET pin may be
used to ensure Vdd has risen to a point where the
ICU can operate correctly before the user program
is run. Reset must be set to Vdd in working mode.
An internal Pull up resistor guarantees that the
RESET pin is at level “1” when no HALT or Power-
On events occur.
for more details.
6.2.2 Reset Procedures. After the Reset pin is
set to Vdd or following a Power-On Reset event,
the device is not started until the external supply
voltage has reached a threshold level (typical
value Vdd=2.6 V, see electrical characteristics).
Figure 6.2 Reset Block Diagram
RESET
RESET pin (external source)
WATCHDOG (internal source)
POWER ON Reset (Internal source)
PLVD Reset (Internal source)
Vdd
originated
POWER-ON
RESET
See Table 16.9
by
external
4096 x TCLK
and
TCLK = Internal Clock period (100 ns)
CKMOD1:0 = see Option Byte 0 (OSC_CR)
W AKEUP = see Option Byte 7 (W AKEUP)
W ATCHDOG
sources
Table 16.15
PLVD
CKMOD1:0
is
PROGRAMMABLE LOW VOLTAGE DETECTOR RESET
INTERNAL CLOCK SOURCES
EXTERNAL CLOCK
After this level has been reached, the internal
oscillator (10 MHZ) is started and a delay period of
4096 clock cycles is initiated, in order to allow the
oscillator to stabilize and to ensure that recovery
has taken place from the Reset state.
If the device has been configured to work with the
internal clock, the user program starts, otherwise
the Option Byte 7 (WAKEUP) is read and another
count starts before running the user program. The
duration of the count depends on the contents of
the Option Byte 7 (WAKEUP), that works as a
prescaler, according to the following formula:
This delay has been introduced in order to ensure
that the oscillator has become stable after its
restart.
If the Reset is generated by the PLVD or the
Watchdog, the oscillator is not turned off; for this
reason the CPU is then restarted immediately,
without the delay.
After a RESET procedure is completed, the core
reads the instruction stored in the first 3 bytes of
the Program/Data Memory, which contains a
JUMP instruction to the first instruction of the user
program.
generates this Jump instruction with the first
instruction address.
Delay
(W AKEUP+1) x
4096 x TCLK
=
The
WATCHDOG RESET
4096
Assembler
WAKEUP
ST52510xx ST52513xx
tool
+
1
automatically
INTERNAL RESET
Tclk
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