ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 105

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

15.5 SPI Register Description
In the following sections describe the registers
used by the SPI.
15.5.1 SPI Configuration Registers.
SPI Control Register (SPI_CR)
Configuration Register 20 (014h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: SPIE Serial peripheral interrupt enable.
Bit 6: SPE Serial peripheral output enable.
Note: The SPE bit is cleared by reset, so the SPI
peripheral is not initially connected to the pins.
Bit 5: SPR2 Divider Enable.
Note: This bit has no effect in slave mode.
Bit 4: MSTR Master/Slave mode select.
SPIE
7
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see
Mode
0: I/O port connected to pins
1: SPI alternate functions connected to pins
This bit is set and cleared by software and it
is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
Table
0: Divider by 2 enabled
1: Divider by 2 disabled
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see
Mode
0: Slave mode is selected
1: Master mode is selected, the function of
SPE
SPIF=1 or MODF=1 in SPI_STATUS_CR
the SCK pin changes from an input to an
output and the functions of the MISO and
MOSI pins are reversed.
Fault).
15.1.
Fault).
SPR2
MSTR
CPOL
Section 15.4.5 Master
Section 15.4.5 Master
CPHA
SPR1
SPR0
0
Bit 3: CPOL Clock polarity.
Note: SPI must be disabled by resetting the SPE
bit if CPOL is changed at the communication byte
boundaries.
Bit 2: CPHA Clock phase.
Bit 1-0: SPR1-SPR0 Serial peripheral rate.
Remark: It is recommended to write the SPI_CR
register after the SPI_STATUS_CR register when
working in master mode, vice versa when working
in slave mode.
Table 15.1 Serial Peripheral Baud Rate
1) This configuration is allowed only for master transmit, not for
master or slave receive.
SPI Control-Status Register (SPI_STATUS_CR)
Configuration Register 21 (015h) Read/Write
Reset Value: 0000 0000 (00h)
SPIF
7
Serial Clock
This bit is set and cleared by software. This
bit determines the steady state of the serial
Clock. The CPOL bit affects both the master
and slave modes.
0: The steady state is a low value at the SCK
1: The steady state is a high value at the SCK
This bit is set and cleared by software.
0: The first clock transition is the first data
1: The second clock transition is the first
These bits are set and cleared by software.
Used with the SPR2 bit, they select one of six
baud rates to be used as the serial clock
when the device is a master (see
These 2 bits have no effect in slave mode.
f
WCOL
f
f
f
CKM
f
f
CKM
CKM
CKM
pin.
pin.
capture edge.
capture edge.
CKM
CKM
/2
/16
/32
/64
/4
/8
1)
OR
MODF
ST52510xx ST52513xx
SPR2
1
0
0
1
0
0
-
SOD
SPR1
0
0
0
1
1
1
Table
SSM
SPR0
105/136
15.1).
0
0
1
0
0
1
SSI
0