ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 82

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

ST52510xx ST52513xx
13 SERIAL COMMUNICATION INTERFACE
The
integrated into ST52F510/F513 provides a general
purpose shift register peripheral, several widely
distributed devices to be linked, through their SCI
subsystem. SCI gives a serial interface providing
communication with the speed from less than 300
up to over 115200 baud, and a flexible character
format.
SCI is a full-duplex UART-type asynchronous
system with standard Non Return to Zero (NRZ)
format for the transmitted/received bit. The length
of the transmitted word is 10/11 bits (1 start bit, 8/
9 data bits, 1 stop bit).
SCI is composed of three modules: Receiver,
Transmitter and Baud-Rate Generator.
13.1 SCI Receiver block
The
synchronization of the serial data stream and
stores the data characters. The SCI Receiver is
mainly composed of two sub-systems: Recovery
Buffer Block and SCDR_RX Block.
SCI receives data deriving from the RX pin and
drives the Recovery Buffer Block, which is a high-
speed shift register operating at a clock frequency
(CLOCK_RX) 16 times higher than the fixed baud
rate (CLOCK_TX). This sampling rate, higher than
the Baud Rate clock, detects the START condition,
Noise error and Frame error.
When the SCI Receiver is in IDLE status, it is
waiting for the START condition, which is obtained
with a logic level of 0, consecutive to a logic level
1. This condition is detected if, with the fixed
Figure 13.2 SCI Block Diagram
82/136
Serial
SCI
Program/Data
Register File
Receiver
Memory
Communication
LDPR/LDPE/LDPI
block
LDRI
Interface
manages
MCLK
OR
IR
(SCI)
the
SCI Receiver
SCI Transmitter
sampling time, a logic level 0 is sampled after three
logic levels of 1.
The recognition of the START bit forces the SCI
Receiver Block to start a data acquisition
sequence.
The data acquisition sequence is configured by the
apposite Configuration Register, allowing the
following data frame formats (see
Figure 13.1 SCI transmitted word structures
■
■
■
■
The parity bit (if used) can be configured for even
or odd parity check. If the 9-bit length format is
configured, this bit is used in transmission for the
ninth bit (see below). The ninth bit received can be
read in the R8 bit of the SCI Status Register,
address 37 (035h) bit 2 (see
Baud-Rate
Generator
SCDR_RX
SCDR_TX
8 bit length, 1 stop bit, no parity bit
8 bit length, 2 stop bit, no parity bit
8 bit length, 1 stop bit, with parity bit
9 bit length, 1 stop bit, no parity bit
RECOVERY BUFFER
STOP
10
SHIFT REGISTER
SCI
STOP
9
9
8
8
7
7
6
6
DATA
DATA
5
5
4
4
Figure
RX
3
3
TX
Figure
2
2
13.3).
1
1
13.1):
START
START
0
0