ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 61

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

Example 1:
IF Input
is codified by the following instructions:
Example 2, the priority of the operator is fixed by the brackets:
IF (Input
At the end of the fuzzy rules related to the current Fuzzy Variable, by using the instruction OUT reg, the
specified register is written with the computed value. Afterwards, the control of the algorithm returns to the
CU. The next Fuzzy Variable evaluation must start again with a FUZZY instruction.
ISNOT 1 1 calculates the NOT
FZAND
IS 4 12
FZOR
IS 3 8
CON crisp
(
IS 3 1
FZAND
ISNOT 4 15 calculates the NOT
)
FZOR
(
IS 1 6
FZOR
ISNOT 2 14 calculates the NOT
)
CON crisp
1
3
IS NOT Mbf
IS Mbf
1
2
implements the operation AND between the previous and the next alpha value evaluated
fixes the
implements the operation OR between the previous and the next alpha value evaluated
fixes the
multiplies the result of the last
parenthesis open to change the priority
fixes the
implements the operation AND between the previous and the next alpha value evaluated
parenthesis closed
implements the operation OR between the previous and the next alpha value evaluated
parenthesis open to change the priority
fixes the
implements the operation OR between the previous and the next alpha value evaluated
parenthesis closed
multiplies the result of the last
1
AND Input
1
AND Input
value of Input
value of Input
value of Input
value of Input
4
IS NOT Mbf
4
is Mbf
value of Input
value of Input
value of Input
4
3
3
1
with Mbf
with Mbf
12
with Mbf
with Mbf
15
OR Input
) OR (Input
operation with the crisp value crisp
operation with the crisp value crisp
12
8
1
1
6
and stores the result in internal registers
4
6
with Mbf
and stores the result in internal registers
and stores the result in internal registers
and stores the result in internal registers
3
with Mbf
with Mbf
IS Mbf
1
IS Mbf
1
15
14
8
and stores the result in internal registers
THEN Crisp
6
and stores the result in internal registers
and stores the result in internal registers
OR Input
6
1
IS NOT Mbf
ST52510xx ST52513xx
1
2
14
) THEN Crisp
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