ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 92

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

ST52510xx ST52513xx
Figure 14.3 Transfer Sequencing
92/136
7-bit Slave receiver:
7-bit Slave transmitter:
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
10-bit Slave transmitter:
10-bit Master transmitter:
10-bit Master receiver:
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, S
EVx=Event (with interrupt if ITE=1)
S Address A
S Address A
S Header
S
S
S
EV5
EV5
EV5
EV1: EVF=1, ADSL=1, cleared by reading I2C_SR1 register.
EV2: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IN register.
EV3: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV3-1: EVF=1, AF=1, BTF=1, SCL=0; AF is cleared by reading I2C_SR2. BTF is cleared
by releasing the lines (STOP=1,STOP=0) or by readyng I2C_SR1 and writing I2C_OUT register
(I2C_OUT=FFh).Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
I2C_SR1 and I2C_SR2 registers can be read only after the falling edge of the ninth data clock cycle
EV4: EVF=1, STOPF=1, cleared by reading I2C_SR2 register.
EV5: EVF=1, SB=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV6: EVF=1, cleared by reading I2C_SR1 register followed by writing I2C_CR (for example PE=1)
EV7: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IN register.
EV8: EVF=1, BTF=1, cleared by reading I2C_SR1, followed by writing I2C_OUT register or an S
EV9: EVF=1, ADD10=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT registe
Address
Address
Header
A
EV1
EV1
Address A
A
A
A
S
r
Data1
Data1
EV9
EV6
EV6 EV8
Header
S
r
Address A
Data1
EV5
EV1
A
A
A
Data1
Header
EV2
EV3
Data1
EV1
A
Data2
Data2
EV6 EV8
EV7
Data1
A
A
A
EV8
Data2
EV6
EV2
A
A
A
Data1
Data2
Data1
EV2
EV3
EV3
.....
A
EV7
DataN
.....
.....
A
r
.....
A
=Intermediate Start without a previous Sto
A
EV8
EV8
DataN
DataN
.....
DataN
EV7
A
.....
.....
DataN
.....
EV2
NA
A
NA
DataN
DataN
DataN
EV2
EV3-1
P
EV3-1
NA
EV4
P
EV7
A
P
A
P
A
EV4
EV4
EV8
EV8
P
EV4
EV7
P
P
P
r
.