ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 84

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

ST52510xx ST52513xx
13.2 SCI Transmitter Block
The SCI Transmitter Block consists of the following
blocks:
synchronized, respectively, with the clock master
signal (fCKM) and the CLOCK_TX.
The whole block receives the settings for the
following
Configuration Register:
■
■
■
■
In case of 9 bit frame transmission, the most
significative bit arrives through the bit PAR/T8 (bit
2) of the SCI_CR1 Configuration Register. In an 8-
bit transmission, instead, this bit is used to
configure the data format: in particular to choose
the polarity control (even or odds) to implement the
parity check (see above).
After a RESET, the SCDR_TX block is in IDLE
state until it receives an enabling signal by writing
the TXSTRT bit of the SCI_CR2 Configuration
Register.
The data is loaded on the Peripheral Register
SCI_OUT (address 23 017h) by using the
instruction
transmission is enabled (TXTSTRT bit of the
SCI_CR2 configuration register), the data to be
transmitted is transferred from the Output Register
to SCDR_TX block and the TXEM flag (bit 1) of the
SCI Status Register is reset to 0 to indicate
SCDR_TX block is full.
If the core supplies new data, this could not be
loaded in the SCDR_TX block until the current data
has not been unloaded on the Shift Register block.
Meaning that only when TXEM is 1 data can be
loaded in the SCDR_TX Block.
When the SHIFT REGISTER Block loads the data
to be transmitted on an internal buffer, the TXEND
flag (bit 0) of the SCI Status Register is reset to 0
to indicate the beginning of a new transmission. At
the end of transmission TXEND is set to 1, allowing
new data coming from SCDR_TX to be loaded in
the SHIFT REGISTER.
It is important to underline that TXEND = 1 does
not mean SCDR_TX is ready to receive a new
data. For this reason, it is better to utilize the TXEM
signal to synchronize the load instruction to the
SCI TRANSMITTER block
If the TXSTRT bit is reset, the transmission is
stopped, but the SCI Transmitter block completes
the transmission in progress before resetting.
84/136
8 bit length, 1 stop bit, no parity bit
8 bit length, 2 stop bit, no parity bit
8 bit length, 1 stop bit, with parity bit
9 bit length, 1 stop bit, no parity bit
SCDR_TX
transmission
LPPR,
LDPI
and
modes
SHIFT
or
LDPE.
through
REGISTER,
If
the
the
13.3 Baud Rate Generator Block
The Baud Rate Generator Block performs the
division of the clock master signal (fCKM) in a set
of synchronism frequencies for the serial bit
reception/transmission on the external line.
Reception frequency (CLOCK_RX) is 16 times
higher
(CLOCK_TX).
To adapt the Baud Rate Generator to the clock
master frequency supplied by the user, a 12-bit
Prescaler must be programmed by loading the
Configuration Registers SCI_CR2 (PRESC_H bit
11:8 of the 12 bit prescaler) and SCI_CR3
(PRESC_L bit 7:0 of the 12 bit prescaler). The
prescaler allows the programming of all standard
Baud Rates by using the most common clock
master sources.
The Prescaler value can be obtained by the
following formula:
Where fCKM is the clock master frequency
(expressed in Hz) and BAUD is the desired Baud
Rate (expressed in bit/second). The obtained
value is rounded to the nearest integer value. This
rounding can cause an error in the obtained Baud
Rate. This error must be lower than 3%. To verify
that the PRESC value satisfies this constrain, the
obtained Baud Rate must be computed by
inverting the previous formula:
then the following relation can be used to verify
that the difference with the desired Baud Rate is
lower than 3%:
Table 13.1
values for common clock master frequencies. To
get more precision in Baud Rate, standard quartz
frequencies for serial communication can be used.
The corresponding Prescaler values for these
frequencies are showed in the
PRESC
than
BAUD
------------------------------------------ -
BAUD BAUD
shows the recommended Prescaler
=
BAUD
the
round
=
–
------------------------------- -
16
transmission
CKM
----------------------------- -
16
PRESC
CKM
Table
BAUD
0.03
13.2.
frequency