ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 93

ST52F513G3M6

Manufacturer Part Number
ST52F513G3M6
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST52F513G3M6

Cpu Family
ST52
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Program Memory Type
Flash
Program Memory Size
8KB
Total Internal Ram Size
256Byte
# I/os (max)
22
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
SO
Lead Free Status / Rohs Status
Compliant

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Figure 14.4 Event Flags and Interrupt Generation
Note: The I
the corresponding Enable Control Bit (ITE) is set and the Interrupt Mask bit (MSKI2C) in the INT_MASK
Configuration Register is unmasked (set to 1, see Interrupts Chapter).
10-bit Address Sent Event (Master Mode)
End of Byte Transfer Event
Address Matched Event (Slave Mode)
Start Bit Generation Event (Master Mode)
Acknowledge Failure Event
Stop Detection Event (Slave Mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
*
EVF can also be set by EV6 or an error from the I2C_SR2 register.
STOPF
ADD10
ARLO
BERR
ADSL
BTF
*
SB
2
AF
C interrupt events are connected to the same interrupt vector. They generate an interrupt if
Interrupt Event
ITE
STOPF
ADD10
ADSEL
Event
ARLO
BERR
Flag
BTF
SB
AF
Control
Enable
ITE
Bit
ST52510xx ST52513xx
INTERRUPT
EVF
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
from
Exit
Halt
No
No
No
No
No
No
No
No
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