ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 51

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

Table 6.1 Recommended Gain Stages for the most common frequencies
Internal Oscillator Calibration (OSC_SET)
Option Byte 2 (02h)
Bit 7-6: Not Used
Bit 5-0: OSPAR5-0 Internal Oscillator Parameters
Warning: the maximum configuration value
allowed is 101000 (40). The value corresponding
to the 10 MHz by design is 010100 (20). Loading
values over 40 the oscillator is stopped.
PLVD Control Register (PLVD_CR)
Option Byte 3 (03h)
(1) The recommended values have been chosen to have the best tradeoff between start time and current
(2) Indicative values by design at 25° Celsius, V
7
7
-
-
External Clock
Frequency
consumption. Higher gains give shorter Start times; lower gains give less current consumption.
10 MHz
12 MHz
16 MHz
20 MHz
1 MHz
4 MHz
8 MHz
These bits are used in order to calibrate the
precision of the internal oscillator working
at 10 MHz. The six bits enable some
current generators with steps of 0.05
corresponding to interval of frequency of
100KHz
-
-
OSPAR5 OSPAR4 OSPAR3 OSPAR2 OSPAR1 OSPAR0
-
.
-
Gain Stages
Recommend
-
0
1
1
3
3
6
6
8
1)
-
PLVD1
CKPAR2-0
DD
PLVD0
000
001
001
101
101
0
0
011
011
=2.6 V. Not Tested in production.
111
A
Bit 7-2: Not Used
Bit 1-0: PLVD1-0 PLVD detection levels
Wake-Up Time Prescaler (WAKEUP)
Option Byte 7 (07h)
Bit 7-0: WK7-0 Wake-up prescaler
Warning: If the internal clock is used as clock
source the prescaler is not used.
WK7
7
Delay
00: Lowest detection level
01: Highest detection level
10: PLVD disabled
11: Medium detection level
This byte determinates the time delay for
the stabilization of the oscillator after an
External Reset or a POR and after the
wake-up from Halt. The time delay is
computed according to the following
formula:
WK6
Start Times
Oscillation
=
367 s
110 s
352 s
165 s
84 s
75 s
79 s
4096
WK5
-
2)
WK4
WAKEUP
ST52510xx ST52513xx
WK3
Settling Times for
40% duty-cycle
WK2
+
27 s
10 s
11 s
9 s
5 s
8 s
7 s
1
-
WK1
Tclk
51/136
2)
WK0
0