ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet - Page 43

• Manufacturer Part Number: ST52F513G3M6
• Manufacturer: STMicroelectronics

Specifications of ST52F513G3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 22
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

5.3 Interrupt Sources
ST52F510/F513
generated by the internal peripherals or generated
by software by the TRAP instruction or coming
from the Port pins. There are two kinds of
interrupts coming from the Port pins: the NMI and
the Ports Interrupts.
NMI (Not Maskable Interrupt) is associated with pin
PA7 when it is configured as Alternate Function.
This interrupt source doesn’t have a configurable
level priority and cannot be masked. The fixed
priority level is lower than the software TRAP and
higher than all the other interrupts. The NMI can be
configured to be active on the rising or the falling
edge.
The Port Interrupts sources are connected with
Port A and Port B pins. The pins belonging to the
same Port are associated with the same interrupt
vector: there is one vector for Port A and one for
Port B. In order to use one port pin as interrupt, it
must be configured as an interrupt source (see I/O
Ports chapter). In this manner, up to 16 Port
Interrupt sources are available. By reading the Port
the sources that belong to the same Port can be
discriminated.
configured to be active on the rising or the falling
edge, by using the INT_POL register.
Warning: changing the NMI or Port Interrupt
polarity an interrupt request is generated.
All the interrupt sources are filtered, in order to
avoid false interrupt requests caused by glitches.
The Trap instruction is something between a
interrupt and a call: it generated an interrupt
request at top priority level and the control is
passed to the associated interrupt routine which
vector is located in the fixed addresses 31-32. This
routine cannot be interrupted and it is serviced
even if the interrupts are globally disabled.
Note: Similarly to the CALL instruction, after a
TRAP the flags are not stacked.
Figure 5.3 Example of Interrupt Requests
The
manages
Port
PRIORITY
LEVEL
0
1
2
3
4
5
6
Interrupts
interrupt
MAIN PROGRAM
can
INT2
signals
INT2
INT0
be
INT0
INT4
INT2
INT1
5.4 Interrupt Maskability and Priority Levels
Interrupts can be masked by the corresponding
INT_MASK Configuration Register 0 (00h). An
interrupt is enabled when the mask bit is “1". Vice
versa, when the bit is “0”, the interrupt is masked
and the eventual requests are kept pending.
All the interrupts, with the exception of the NMI and
TRAP that have fixed level priority, have a
configurable priority level. The configuration of the
priority levels is completed by writing three
consecutive Configuration Registers: INT_PRL_L,
INT_PRL_M, INT_PRL_H, addresses from 2 to 4
(02h-04h). The 24 bits of these registers are
divided into 8 groups of three bits: each group is
associated with a priority level. The three bits of
each group are written with the code number
associated with the interrupt source. See
to know the codes.
Warning:
Registers must be programmed with different
values for each 3-bit groups to avoid erroneous
operation. After the RESET the priority registers
are loaded with a default priority configuration.
Each time the priority is modified, each priority
register must be configured with consistent values.
During program execution the interrupt priority can
only be modified within the Main Program: it cannot
be changed within an interrupt service routine. In
addition the interrupts must be disabled by means
of the UDGI instruction. In order to avoid side effect
the interrupts must be disabled before the priority
register configuration.
5.5 Interrupt RESET
When an interrupt is masked, all requests are not
acknowledged and remain pending. When the
pending interrupt is enabled it is immediately
serviced, if it has proper priority. This event may be
undesired; in order to avoid this a RINT instruction
may be inserted followed by the code number that
identifies the interrupt to reset the pending request.
The RINT instruction has no effect if the interrupt is
being serviced
See
INT1
INT2
Table 5.1
INT3
INT3
The
INT4
to know the codes.
MAIN PROGRAM
priority
ST52510xx ST52513xx
levels
Configuration
Table 5.1
43/136