LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 137

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
DDRM
DDRM
DDRM
DDRM
DDRM
Field
4
3
2
1
0
Port M data direction—
This register controls the data direction of pin 4.
The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an input. Depending on the configuration
of the enabled routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not
change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 3.
The enabled CAN1 or routed CAN0 forces the I/O state to be an output. Depending on the configuration of the
enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 2.
The enabled CAN1 or routed CAN0 forces the I/O state to be an input. Depending on the configuration of the enabled
routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 1.
The enabled CAN0 forces the I/O state to be an output. In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 0.
The enabled CAN0 forces the I/O state to be an input. In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTM or PTIM registers, when changing the
DDRM register.
Table 2-35. DDRM Register Field Descriptions (continued)
MC9S12XE-Family Reference Manual , Rev. 1.23
NOTE
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
137