LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 162

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x0275

Address 0x0276

Write: Anytime.

Port AD0 reduced drive—Select reduced drive for Port AD0 outputs

This register conﬁgures the drive strength of Port AD0 output pins 7 through 0 as either full or reduced independent

of the function used on the pins. If a pin is used as input this bit has no effect.

1 Reduced drive selected (approx. 1/5 of the full drive strength).

0 Full drive strength enabled.

Port AD0 pull device enable—Enable pull devices on input pins

These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect

if the pin is used as an output. Out of reset no pull device is enabled.

1 Pull device enabled.

0 Pull device disabled.

Port AD0 Reduced Drive Register 1 (RDR1AD0)

Port AD0 Pull Up Enable Register 0 (PER0AD0)

Figure 2-72. Port AD0 Reduced Drive Register 1 (RDR1AD0)

Figure 2-73. Port AD0 Pull Device Up Register 0 (PER0AD0)

Table 2-70. RDR1AD0 Register Field Descriptions

Table 2-71. PER0AD0 Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Access: User read/write

Freescale Semiconductor