LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 152

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x0266

Address 0x0267

Write: Anytime.

Read: Anytime.

Port H interrupt enable—

This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port H.

1 Interrupt is enabled.

0 Interrupt is disabled (interrupt ﬂag masked).

Port H interrupt ﬂag—

Each ﬂag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the

state of the PPSH register. To clear this ﬂag, write logic level 1 to the corresponding bit in the PIFH register. Writing

a 0 has no effect.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).

0 No active edge pending.

Port H Interrupt Enable Register (PIEH)

Port H Interrupt Flag Register (PIFH)

Figure 2-57. Port H Interrupt Enable Register (PIEH)

Figure 2-58. Port H Interrupt Flag Register (PIFH)

Table 2-55. PPSP Register Field Descriptions

Table 2-56. PPSP Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Access: User read/write

Freescale Semiconductor