LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 164

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x0279

Address 0x027A

Write: Anytime.

Port AD1 general purpose input/output data—Data Register

This register is associated with ATD1 analog inputs AN[7:0] on PAD[23:16], respectively.

When not used with the alternative function, these pins can be used as general purpose I/O.

If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise

the buffered pin input state is read.

Port AD1 data direction—

This register controls the data direction of pins 15 through 8.

1 Associated pin is conﬁgured as output.

0 Associated pin is conﬁgured as input.

Port AD1 Data Register 1 (PT1AD1)

Port AD1 Data Direction Register 0 (DDR0AD1)

Figure 2-77. Port AD1 Data Direction Register 0 (DDR0AD1)

Table 2-75. DDR0AD1 Register Field Descriptions

Figure 2-76. Port AD1 Data Register 1 (PT1AD1)

Table 2-74. PT1AD1 Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Access: User read/write

Freescale Semiconductor