LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 689

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.4
Figure 18-19
control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger
interface.
18.4.1
As shown in
16-bit modulus down-counters and two 8-bit modulus down-counters. The 16-bit timers are clocked with
two selectable micro time bases which are generated with 8-bit modulus down-counters. Each 16-bit timer
is connected to micro time base 0 or 1 via the PMUX[3:0] bit setting in the PIT Multiplex (PITMUX)
register.
A timer channel is enabled if the module enable bit PITE in the PIT control and force load micro timer
(PITCFLMT) register is set and if the corresponding PCE bit in the PIT channel enable (PITCE) register
is set. Two 8-bit modulus down-counters are used to generate two micro time bases. As soon as a micro
time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter
will load its start value as specified in the PITMTLD0 or PITMTLD1 register and will start down-counting.
Freescale Semiconductor
PCNT[15:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Bus
Clock
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
15:0
Functional Description
PFLMT
[0]
[1]
Timer
PIT Count Bits 15-0 — These bits represent the current 16-bit modulus down-counter value. The read access
for the count register must take place in one clock cycle as a 16-bit access.
Figure 18-1
shows a detailed block diagram of the PIT module. The main parts of the PIT are status,
PITCFLMT Register
PITFLT Register
PITMUX Register
PITMLD0 Register
8-Bit Micro Timer 0
PITMLD1 Register
8-Bit Micro Timer 1
and
Figure 18-19. PIT24B4C Detailed Block Diagram
Figure
Table 18-10. PITCNT0–3 Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.23
4
4
18-19, the 24-bit timers are built in a two-stage architecture with four
PMUX0
PFLT0
PFLT2
PFLT1
PFLT3
[1]
[2]
[3]
Timer 0
Timer 1
Timer 2
Timer 3
PITLD0 Register
PITCNT0 Register
PITLD1 Register
PITCNT1 Register
PITLD2 Register
PITCNT2 Register
PITLD3 Register
PITCNT3 Register
Description
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
time-
out 3
time-
out 3
time-out 0
time-out 1
PIT24B4C
PITTF Register
PITINTE Register
Interrupt /
Trigger Interface
Hardware
Trigger
Interrupt
Request
4
4
689