LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 684

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)

Read: Anytime

Write: Anytime

Module Base + 0x0002

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0. If PCE is cleared, the PIT

channel is disabled and the corresponding ﬂag bit in the PITTF register is cleared. When PCE is set, and if the

PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-

0 The corresponding PIT channel is disabled.

1 The corresponding PIT channel is enabled.

PIT Channel Enable Register (PITCE)

Figure 18-5. PIT Channel Enable Register (PITCE)

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 18-4. PITCE Field Descriptions

Freescale Semiconductor