LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 222
LFEBS12UB
Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Specifications of LFEBS12UB
Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 3 Memory Mapping Control (S12XMMCV4)
3.4.4.1
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
3.5
3.5.1
CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
222
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
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CPU always has priority over BDM and XGATE.
XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
for its duration.
XGATE has priority over BDM.
BDM has priority over CPU and XGATE when its access is stalled for more than 128 cycles. In the
later case the suspect master will be stalled after finishing the current operation and the BDM will
gain access to the bus.
In emulation modes all internal accesses are visible on the external bus as well and the external bus
is used during access to the PRU registers.
Initialization/Application Information
EBI
XGATE
CALL and RTC Instructions
XBUS3
Master Bus Prioritization regarding access conflicts on Target Buses
XGATE
XBUS1
FLASH
DBG
FTM
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 3-23. MMC Block Diagram
MMC “Crossbar Switch”
EEE
XBUS0
CPU
S12X0
resources
BDM
BDM
S12X1
XSRAM
XRAM
Freescale Semiconductor
FLEXRAY
IPBI
S12X2
XBUS2
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