LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 166

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x027C

Address 0x027D

Write: Anytime.

Port AD1 reduced drive—Select reduced drive for Port AD1 outputs

This register conﬁgures the drive strength of Port AD1 output pins 15 through 8 as either full or reduced independent

of the function used on the pins. If a pin is used as input this bit has no effect.

1 Reduced drive selected (approx. 1/5 of the full drive strength).

0 Full drive strength enabled.

Port AD1 reduced drive—Select reduced drive for Port AD1 outputs

This register conﬁgures the drive strength of Port AD1 output pins 7 through 0 as either full or reduced independent

of the function used on the pins. If a pin is used as input this bit has no effect.

1 Reduced drive selected (approx. 1/5 of the full drive strength).

0 Full drive strength enabled.

Port AD1 Reduced Drive Register 0 (RDR0AD1)

Port AD1 Reduced Drive Register 1 (RDR1AD1)

Figure 2-79. Port AD1 Reduced Drive Register 0 (RDR0AD1)

Figure 2-80. Port AD1 Reduced Drive Register 1 (RDR1AD1)

Table 2-77. RDR0AD1 Register Field Descriptions

Table 2-78. RDR1AD1 Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Access: User read/write

Freescale Semiconductor