LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 631

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
Module Base + 0x001C to Module Base + 0x001F
Module Base + 0x0014 to Module Base + 0x0017
16.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Freescale Semiconductor
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
AM[7:0]
AC[7:0]
Field
Field
7-0
7-0
Reset
Reset
Figure 16-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
Figure 16-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
W
W
R
R
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
AM7
AM7
0
7
0
7
Table 16-24. CANIDMR0–CANIDMR3 Register Field Descriptions
Table 16-23. CANIDAR4–CANIDAR7 Register Field Descriptions
AM6
AM6
0
6
0
6
MC9S12XE-Family Reference Manual Rev. 1.23
AM5
AM5
0
5
0
5
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
AM4
AM4
Description
0
Description
4
0
4
AM3
AM3
0
3
0
3
AM2
AM2
0
2
0
2
Access: User read/write
Access: User read/write
AM1
AM1
0
1
0
1
AM0
AM0
0
0
0
0
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