LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 993

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is

erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and

the number of phrases. The section to be verified cannot cross a 256 Kbyte boundary in the P-Flash

memory space.

Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will

verify the selected section of Flash memory is erased. The CCIF ﬂag will set after the Erase Verify P-Flash

Section operation has completed.

Freescale Semiconductor

1. As deﬁned by the memory map for FTM512K3.

2. As found in the memory map for FTM512K3.

Erase Verify P-Flash Section Command

Table 26-37. Erase Verify P-Flash Section Command FCCOB Requirements

Table 26-36. Erase Verify Block Command Error Handling

MC9S12XE-Family Reference Manual , Rev. 1.23

Set if CCOBIX[2:0] != 000 at command launch

Set if a Load Data Field command sequence is currently active

Set if an invalid global address [22:16] is supplied

Set if any errors have been encountered during the read

Set if any non-correctable errors have been encountered during the read

Global address [15:0] of the ﬁrst phrase to be veriﬁed

Number of phrases to be veriﬁed

FCCOB Parameters

Global address [22:16] of

Error Condition

Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)

a P-Flash block