LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 257

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4.3
All read and write accesses to PRR addresses take two bus clock cycles independent of the operating mode.
If writing to these addresses in emulation modes, the access is directed to both, the internal register and
the external resource while reads will be treated external.
The XEBI control registers also belong to this category.
5.4.4
In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI
supports stretched external bus accesses (wait states) for each external address range related to one of the
4 chip select lines individually.
This feature is available in normal expanded mode and emulation expanded mode for accesses to all
external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2
cycles, respectively.
Stretched accesses are controlled by:
The EXSTRx[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch
cycles. If the external wait feature is enabled, the minimum number of additional stretch cycles is 2. An
arbitrary amount of stretch cycles can be added using the EWAIT input.
EWAIT needs to be asserted at least for a minimal specified time window within an external access cycle
for the internal logic to detect it and add a cycle (refer to electrical characteristics). Holding it for additional
cycles will cause the external bus access to be stretched accordingly.
Write accesses are stretched by holding the initiator in its current state for additional cycles as programmed
and controlled by external wait after the data have been driven out on the external bus. This results in an
extension of time the bus signals and the related control signals are valid externally.
Read data are not captured by the system in normal expanded mode until the specified setup time before
the RE rising edge.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
1. EXSTR1[2:0] and EXSTR0[2:0] bits in the EBICTL1 register configuring a fixed amount of
2. Activation of the external wait feature for each CSx line MMCCTL0 register
3. Assertion of the external EWAIT signal when at least one CSx line is configured for EWAIT
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
RW
stretch cycles individually for each CSx line in MMCCTL0
Accesses to Port Replacement Registers
Stretched External Bus Accesses
Table 5-18. Interleaved Read-Write-Read Accesses (1 Cycle) (continued)
...
...
...
...
...
...
MC9S12XE-Family Reference Manual Rev. 1.23
addr 0
high
?
?
1
iqstat -1
acc 0
low
?
1
z
z
addr 1
data 0
high
0
z
iqstat 0
acc 1
ivd 0
low
Chapter 5 External Bus Interface (S12XEBIV4)
0
(write) data 1
(write) data 1
addr 2
high
1
iqstat 1
acc 2
low
x
z
z
1
...
...
...
...
...
...
...
257