LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 974

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)
26.3.2.8
The FERSTAT register reflects the error status of internal Flash operations.
All flags in the FERSTAT register are readable and only writable to clear the flag.
974
MGSTAT[1:0]
MGBUSY
ACCERR
Offset Module Base + 0x0007
Reset
FPVIOL
RSVD
Field
CCIF
1–0
7
5
4
3
2
W
R
ERSERIF
Flash Error Status Register (FERSTAT)
7
0
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see
command or when errors are encountered while initializing the EEE buffer ram during the reset sequence.
While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by
writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash memory during a command write sequence. The FPVIOL bit is cleared
by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not
possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0) or is handling internal EEE operations
Reserved Bit — This bit is reserved and always reads 0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
is detected during execution of a Flash command or during the Flash reset sequence. See
“Flash Command
= Unimplemented or Reserved
PGMERIF
0
6
Figure 26-12. Flash Error Status Register (FERSTAT)
Description,” and
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 26-17. FSTAT Field Descriptions
0
0
5
Section 26.6,
EPVIOLIF
0
4
Description
“Initialization” for details.
ERSVIF1
.
0
3
Section
ERSVIF0
0
2
26.4.1.2) or issuing an illegal Flash
Freescale Semiconductor
DFDIF
0
1
Section 26.4.2,
SFDIF
0
0
.