LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 514

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
13.3.2.4
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
514
Module Base + 0x0003
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
ACMPIE
ASCIE
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
DJM
1
0
7
W
R
DJM
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), ATD Compare
Result Register Data Justification — Result data format is always unsigned. This bit controls justification of
conversion data in the result registers.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Table 13-10
ATD Control Register 3 (ATDCTL3)
0
7
Interrupt will be requested whenever any of the respective CCF flags is set.
= Unimplemented or Reserved
gives examples ATD results for an input signal range between 0 and 5.12 Volts.
S8C
0
6
ETRIGLE
Table 13-7. ATDCTL2 Field Descriptions (continued)
Figure 13-6. ATD Control Register 3 (ATDCTL3)
0
0
1
1
Table 13-8. External Trigger Configurations
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 13-9. ATDCTL3 Field Descriptions
S4C
5
1
ETRIGP
0
1
0
1
S2C
0
4
Description
Description
External Trigger Sensitivity
S1C
0
3
Falling edge
Rising edge
High level
Low level
FIFO
2
0
Freescale Semiconductor
FRZ1
0
1
FRZ0
0
0