LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 768

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 21 Serial Peripheral Interface (S12SPIV5)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Module Base +0x0001

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by

asserting the SSOE as shown in

progress and force the SPI system into idle state.

LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and

writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit

will abort a transmission in progress and force the SPI system into idle state.

0 Data is transferred most signiﬁcant bit ﬁrst.

1 Data is transferred least signiﬁcant bit ﬁrst.

SPI Control Register 2 (SPICR2)

= Unimplemented or Reserved

Table 21-2. SPICR1 Field Descriptions (continued)

Figure 21-4. SPI Control Register 2 (SPICR2)

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 21-3. SS Input / Output Selection

SS input with MODF feature

21-3. In master mode, a change of this bit will abort a transmission in

SS is slave select output

SS not used by SPI

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