LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 183

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Each cell represents one register with individual conﬁguration bits

This register holds the value driven out to the pin if the pin is used as a general purpose I/O.

Writing to this register has only an effect on the pin if the pin is used as general purpose output. When

reading this address, the buffered state of the pin is returned if the associated data direction register bit is

If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This

is independent of any other conﬁguration

This is a read-only register and always returns the buffered state of the pin

This register deﬁnes whether the pin is used as an input or an output.

If a peripheral module controls the pin the contents of the data direction register is ignored

Freescale Semiconductor

Data register (PORTx, PTx)

Input register (PTIx)

Data direction register (DDRx)

Table 2-103. Register availability per port

MC9S12XE-Family Reference Manual , Rev. 1.23

Chapter 2 Port Integration Module (S12XEPIMV1)