LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 811

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit:

PRNT = 1 : Prescaler = PTPS[7:0] + 1

This section provides a complete functional description of the timer TIM16B8CV2 block. Please refer to

the detailed timer block diagram in

Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Functional Description

Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.

These are effective only when the PRNT bit of TSCR1 is set to 1.

in this case.

The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter

stages equal zero.

Table 22-24. Precision Timer Prescaler Selection Examples when PRNT = 1

MC9S12XE-Family Reference Manual Rev. 1.23

Table 22-23. PTPSR Field Descriptions

Figure 22-30

as necessary.

Chapter 22 Timer Module (TIM16B8CV2) Block Description

shows some selection examples