LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 79

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.4.2.4
This mode is entered if the CPU executes the STOP instruction when the XGATE is not executing a thread
and the XGFACT bit in the XGMCTL register is set. The oscillator remains active and any enabled
peripherals continue to function.
1.4.2.5
This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in
system wait mode. For further power consumption the peripherals can individually turn off their local
clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that is not masked and is not routed to XGATE
ends system wait mode.
1.4.2.6
Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save
power.
1.4.3
The enhanced capture timer, pulse width modulator, analog-to-digital converters, and the periodic interrupt
timer provide a software programmable option to freeze the module status when the background debug
module is active. This is useful when debugging application software. For detailed description of the
behavior of the ATD0, ATD1, ECT, PWM, and PIT when the background debug module is active consult
the corresponding Block Guides.
1.4.4
To facilitate system integrity the MCU can run in Supervisor state or User state. The System States strategy
is implemented by additional features on the S12X CPU and a Memory Protection Unit. This is designed
to support restricted access for code modules executed by kernels or operating systems supporting access
control to system resources.
The current system state is indicated by the U bit in the CPU condition code register. In User state certain
CPU instructions are restricted. See the CPU reference guide for details of the U bit and of those
instructions affected by User state.
In the case that software task accesses resources outside those defined for it in the MPU a non-maskable
interrupt is generated.
1.4.4.1
This state is intended for configuring the MPU for different tasks that are then executed in User state,
returning to Supervisor state on completion of each task. This is the default ’state’ following reset and can
be re-entered from User state by an exception (interrupt). If the SVSEN bit in the MPUSEL register of the
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
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Freeze Mode
System States
XGATE Fake Activity Mode
Wait Mode
Run Mode
Supervisor State
MC9S12XE-Family Reference Manual Rev. 1.23
Chapter 1 Device Overview MC9S12XE-Family
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