LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 744

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 20 Serial Communication Interface (S12SCIV5)

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the

transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor.

The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is

synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the

transmitter. The receiver has an acquisition rate of 16 samples per bit time.

Baud rate generation is subject to one source of error:

When IREN = 0 then,

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Integer division of the bus clock may not give the exact target frequency.

SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])

Baud Rate Generation

lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz.

Table 20-16. Baud Rates (Example: Bus Clock = 25 MHz)

1. The address bit identiﬁes the frame as an address

character. See

MC9S12XE-Family Reference Manual , Rev. 1.23

Section 20.4.6.6, “Receiver

Freescale Semiconductor