LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 468

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
START_XGATE
DUMMY_ISR
XGATE_DATA_FLASH
XGATE_DATA_SCI
XGATE_DATA_IDX
XGATE_DATA_MSG
XGATE_CODE_FLASH
XGATE_CODE_DONE
XGATE_CODE_FLASH_END
XGATE_DUMMY_ISR_XG
10.9.3
To simplify the implementation of a program stack the XGATE can be configured to set RISC core register
R7 to the beginning of a stack region before executing a thread. Two separate stack regions can be defined:
One for threads of priority level 7 to 4 (refer to
468
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Stack Support
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
CPX
BLS
;###########################################
;#
;###########################################
MOVW #XGMCTL_ENABLE, XGMCTL
BRA
;###########################################
;#
;###########################################
RTI
CPU
;###########################################
;#
;###########################################
ALIGN 1
EQU
EQU
DW
EQU
DB
EQU
FCC
DB
;###########################################
;#
;###########################################
ALIGN 1
LDW
LDB
LDB
STB
LDB
STB
CMPL R4,#$0D
BEQ
RTS
LDL
STB
LDL
STB
RTS
EQU
MC9S12XE-Family Reference Manual , Rev. 1.23
#XGATE_CODE_FLASH_END
COPY_XGATE_CODE_LOOP
*
XGATE
*
*-XGATE_DATA_FLASH
SCI_REGS
*-XGATE_DATA_FLASH
XGATE_DATA_MSG
*-XGATE_DATA_FLASH
"Hello World!
$0D
R2,(R1,#XGATE_DATA_SCI)
R3,(R1,#XGATE_DATA_IDX)
R4,(R1,R3+)
R3,(R1,#XGATE_DATA_IDX)
R0,(R2,#(SCISR1-SCI_REGS))
R4,(R2,#(SCIDRL-SCI_REGS))
XGATE_CODE_DONE
R4,#$00
R4,(R2,#(SCICR2-SCI_REGS))
R3,#XGATE_DATA_MSG;reset R3
R3,(R1,#XGATE_DATA_IDX)
(XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG
DUMMY INTERRUPT SERVICE ROUTINE
START XGATE
XGATE CODE
XGATE DATA
Section 10.3.1.5, “XGATE Initial Stack Pointer for
;enable XGATE
;pointer to SCI register space
;string pointer
;ASCII string
;CR
;SCI -> R2
;msg -> R3
;curr. char -> R4
;R3 -> idx
;initiate SCI transmit
;initiate SCI transmit
;disable SCI interrupts
#
#
#
#
Freescale Semiconductor