LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 34

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1 Device Overview MC9S12XE-Family
1.1.5
Figure 1-2
also the location of the internal resources in the memory map.
EEEPROM size is presented like a fixed 256 KByte in the memory map.
34
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
shows S12XE CPU & BDM local address translation to the global memory map. It indicates
Address Mapping
Reserved register space shown in
This register space is reserved for future use. Writing to these locations have
no effect. Read access to these locations returns zero.
0x02C0–0x02EF
0x03C0–0x03CF
0x03D0–0x03FF
0x0200–0x023F
0x0240–0x027F
0x0280–0x02BF
0x02F0–0x02F7
0x02F8–0x02FF
0x0328–0x032F
0x0338–0x033F
0x0368–0x037F
0x0380–0x03BF
0x0400–0x07FF
0x0300–0x0327
0x0330–0x0337
0x0340–0x0367
Address
Table 1-1. Device Register Memory Map (continued)
MC9S12XE-Family Reference Manual , Rev. 1.23
CAN3
PIM (port integration module)
CAN4
ATD0 (analog-to-digital converter 12 bit 16-channel)
Voltage regulator
Reserved
PWM (pulse-width modulator 8 channels)
Reserved
SCI6 (serial communications interface)
SCI7 (serial communications interface)
PIT (periodic interrupt timer)
PIM (port integration module)
XGATE
Reserved
TIM (timer module)
Reserved
Table 1-1
NOTE
Module
is not allocated to any module.
(Bytes)
1024
Size
64
64
64
48
40
40
24
64
16
48
8
8
8
8
8
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