HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 221

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

8.4.2 I/O Mode
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of
these transfers are executed. One address is specified in the memory address register (MAR), the
other in the I/O address register (IOAR). The direction of transfer is determined automatically
from the activation source. The transfer is from the address specified in IOAR to the address
specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the
address specified in MAR to the address specified in IOAR otherwise.
Table 8-6 indicates the register functions in I/O mode.
Table 8-6 Register Functions in I/O Mode
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
Figure 8-2 illustrates how I/O mode operates.
Register
Decremented
Legend
MAR:
IOAR: I/O address register
ETCR: Execute transfer count register
23
23
All 1s
Memory address register
15
MAR
ETCR
7
IOAR
0
0
0
Activated by
SCI 0 Receive-
Data-Full
Interrupt
Destination
address
register
Source
address
register
Transfer counter
Function
207
Other
Activation
Source
address
register
Destination
address
register
transfers
Initial Setting
Destination or
source address
Source or
destination
address
Operation
Incremented or
decremented
once per transfer
Held fixed
Number of
once per
transfer until
H'0000 is
reached and
transfer ends