HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 373

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an
underflow occurs. When buffering is selected, buffer register contents are transferred to the
general register at compare match A3 during up-counting, and when TCNT4 underflows.
General Register Settings in Complementary PWM Mode: When setting up general registers
for complementary PWM mode or changing their settings during operation, note the following
points.
•
•
•
Buffer transfer
signal (BR to GR)
Initial settings
Do not set values from H'0000 to T – 1 (where T is the initial value of TCNT3). After the
counters start and the first compare match A3 event has occurred, however, settings in this
range also become possible.
Changing settings
Use the buffer registers. Correct waveform output may not be obtained if a general register is
written to directly.
Cautions on changes of general register settings
Figure 10-39 shows six correct examples and one incorrect example.
TCNT4
OVF
GR
Figure 10-38 Undershoot Timing
H'0001
H'0000
Buffer transfer
361
Set to 1
Underflow
H'FFFF
Overflow
H'0000
Flag not set
No buffer transfer