HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 239

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

8.4.8 DMAC Bus Cycle
Figure 8-13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (T
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
ø
Address
bus
RD
HWR
LWR
T
1
CPU cycle
T
2
Figure 8-13 DMA Transfer Bus Timing (Example)
T
1
T
2
T
d
T
Source
address
1
DMAC cycle (word transfer)
T
2
225
T
1
T
Destination address
2
T
d
3
), it reads from the source address and
T
1
T
2
T
3
T
1
T
CPU cycle
2
T
1
T
2