HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 595

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

4.
5.
6.
7. During reset (when RES pin input is Low), if MD
The RXD
Before branching to the user program (at address H'F300 in the RAM area), the H8/3048F
terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE
and TE bits in serial control register (SCR) to 0 in channel 1), but the auto-aligned bit rate
remains set in bit rate register BRR1. The transmit data pin (TXD
(in port 9, the P9
data register are set to 1).
When the branch to the user program occurs, the contents of general registers in the CPU are
undetermined. After the branch, the user program should begin by initializing general
registers, especially the stack pointer (SP), which is used implicitly in subroutine calls and at
other times. The stack pointer must be set to provide a stack area for use by the user program.
The other on-chip registers do not have specific initialization requirements.
Transition to boot mode are shown in Figure 18-12, “RAM Areas in Boot Mode.” This is
possible after applying 12 V to pins MD
is erased (startup with Low
internally to maintain boot mode. Boot mode can be erased if the 12 V applied to the MD
pin and the V
•
•
•
vice versa, by instantaneous transfer to 5 V input, the personal computer switches to
operation mode. As a result, the address port or bus control output signal (AS, RD, HWR,
LWR) status changes, so do not these pins as output signals during reset, as the personal
computer internal section needs to be shut down.
When transferring from boot mode to regular mode (V
transfer the erase must be carried out by the reset input personal computer internal boot
mode RES pin. After V
flash memory read setup (t
While in boot mode, if the 12 V applied to the MD
from the RES pin does not occur, the personal computer internal boot mode status will be
maintained and boot mode will continue. In boot mode, if watchdog timer reset occur, the
personal computer internal boot mode is not erased, and despite mode pin status the
internal boot program restarts.
When transferring to boot mode (reset erase timing) or during boot mode operation,
program voltage V
boot mode will not operate correctly. In addition, during boot program operation or
writing and erasing the flash memory, do not interrupt V
1
and TXD
PP
pin is erased, then reset is erased*
1
DDR bit in port 9 data direction register P9DDR and P9
1
lines should be pulled up on-board.
PP
should be within the range 12 V to 0.6 V. If this range is exceeded,
PP
High) timing*
interrupt, erase reset. The time needed until reset vector lead is
FRS
) *
2
.
2
and V
586
1
, mode pin status latches the personal computer
PP
2
1
and restarting. In this case, H8/3048F reset
. However, please note the following.
pin input changes from 0 V to 12 V or
2
pin is erased, as long as reset input
PP
PP
*
12 V, MD
2
.
1
) is in the high output state
1
2
DR bit in port 9
12 V), before
2