HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 251

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

8.5 Interrupts
The DMAC generates only DMA-end interrupts. Table 8-13 lists the interrupts and their priority.
Table 8-13 DMAC Interrupts
Interrupt
DEND0A
DEND0B
DEND1A
DEND1B
Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control
register (DTCR). Separate interrupt signals are sent to the interrupt controller.
The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B.
Figure 8-25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and
DTIE = 1.
The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The
DTME bit does not affect interrupt operations.
Short Address Mode
End of transfer on channel 0A
End of transfer on channel 0B
End of transfer on channel 1A
End of transfer on channel 1B
DTIE
DTE
Figure 8-25 DMA-End Interrupt Logic
Description
237
Full Address Mode
End of transfer on channel 0
—
End of transfer on channel 1
—
DMA-end interrupt
Interrupt Priority
High
Low